1. Field of the Invention
The present invention relates to memory control units, memory control methods and media containing programs for realizing the same. More particularly, the present invention relates to a unit, a method and a medium containing a program, in a circuit controlling memory in which a delay develops depending on order of access thereto such as a dynamic random access memory (DRAM) that transfers data in synchronization with an operation clock to be a basis of operation, i.e., synchronous DRAM (SDRAM), for optimizing the access order to increase an actual bus bandwidth to SDRAM.
2. Description of the Background Art
The SDRAM has been conventionally in existence as one of apparatus for storing data. In SDRAM, burst transmission that continuously transfers data in synchronization with an operation clock can be designated, and the predetermined number of bits which is the smallest unit for read and write (hereinafter, referred to as a word length) can be continuously transferred the previously-specified number of times (hereinafter, referred to as a burst length) in one clock unit. Therefore, SDRAM has excellent usability.
FIG. 27 shows a memory area of a typical SDRAM. A memory area of an SDRAM is generally divided into banks composed of a plurality of pages. The SDRAM shown in FIG. 27 is divided into two banks, i.e., banks 0 and 1 which are each composed of xe2x80x9cnxe2x80x9d pages from a page 0 to a page (nxe2x88x921). Each page is composed of xe2x80x9cmxe2x80x9d columns from a column 0 to a column (mxe2x88x921). Here, n and m are both integers of not less than 1. Since data is read and written column by column, the word length is equal to the number of bits in one column. For example, one column is 8 bits, m is 512, and n is 2048.
FIG. 28 is a state-transition diagram of a typical SDRAM. The SDRAM generally comprises a xe2x80x9csense amplifierxe2x80x9d in each bank. As is clear from FIG. 28, when data stored in a column is read or data is written into a column, data in a page including the column to be read or written is previously transferred to a sense amplifier (activate) in a bank to which the page belongs, afterwhich the data is read or written from/in the sense amplifier (hereinafter, xe2x80x9cread and writexe2x80x9d are simply referred to as xe2x80x9caccessxe2x80x9d). When access is continuously made to columns included in the same page in the same bank, however, data in the corresponding page has been already transferred to the sense amplifier, and therefore it is not necessary to transfer the data again.
Moreover, when a column A included in a page A is accessed and then access is made to a column B included in a page B belonging to the same bank as the page A, it is required to transfer the contents of a sense amplifier previously holding data corresponding to the page A to the page A (precharge) once and then transfer data in the page B to the sense amplifier (activate). Accordingly, when access is continuously made to columns included in different pages in the same bank, it is required to precharge and activate, resulting in a decrease of actual transfer rates.
However, since the memory area of SDRAM is divided into a plurality of banks, the decrease of actual transfer rates can be avoided by accessing different banks in the case of continuous access and performing precharge and activation processing in each bank during accessing of the other bank.
The SDRAM is described in detail, for example, in xe2x80x9cNEC DATASHEET, MOS Integrated Circuit xcexc PD4516421A, 4516821A, and 45116161A for Rev.P 16M-bit Synchronous DRAM (Document number: M12939EJ3V0DS00 (3rd edition), Issue date: April 1998, N CP(K))xe2x80x9d and xe2x80x9cJapanese Patent Laying-Open No.6-76567: Semiconductor Memory Device and Synchronism Type Semiconductor Memory Devicexe2x80x9d.
As a memory control unit for efficiently controlling such a high-performance SDRAM, a unit as described below has been conventionally used. FIG. 29 is a block diagram showing an example of a structure of a conventional memory control unit. In FIG. 29, the conventional memory control unit comprises a transfer-target unit 81, an address generator 82, a command generator 83, a data processor 84, and an SDRAM 85.
The transfer-target unit 81 outputs commands such as a start address, a transfer size, read/write and the like to the address generator 82, to transfer data between the SDRAM 85. The address generator 82 generates a plurality of control signals for a start address, a burst length, read/write and the like based on the commands received from the transfer-target unit 81, and outputs the signals to the command generator 83. The command generator 83 generates control commands such as a clock (CLK), a row address strobe (RAS), a column address strobe (CAS), write enable (WE), addressing and the like based on the control signals received from the address generator 82, and thereby controls the SDRAM 85 and the data processor 84. The data processor 84 transfers read data from the SDRAM 85 to the transfer-target unit 81 according to the control commands received from the command generator 83, and also transfers write data from the transfer-target unit 81 to the SDRAM 85. The SDRAM 85 has features similar to those of a typical SDRAM as described above, and is controlled by the control commands acquired from the command generator 83.
As a memory system for efficiently controlling such a high-performance SDRAM, a system as described below has been conventionally used. FIG. 30 shows an example of a structure of a conventional memory system. In FIG. 30,the conventional memory system comprises transfer-target units 231 to 233, an arbiter 234, an SDRAM controller 235, and an SDRAM 85.
Each of the transfer-target units 231 to 233 outputs a transfer request signal to the arbiter 234 when required to transfer data with the SDRAM 85, and outputs transfer information to the SDRAM controller 235 when a transfer enabling signal is returned from the arbiter 234. When acquiring a transfer request signal from any one of the transfer-target units, the arbiter 234 returns a transfer enabling signal to the transfer-target unit which outputs the transfer request signal. Moreover, when acquiring transfer request signals from a plurality of transfer-target units, the arbiter 234 selects a higher-priority signal among the transfer request signals, then returns a transfer enabling signal to the transfer-target unit which outputs the selected transfer request signal. The same processing is performed to the remaining transfer request signals which are not selected. The SDRAM controller 235 is constituted by the address generator 82, the command generator 83, and the data processor 84 as described above. The SDRAM controller 235 generates control commands such as CLK, RAS, CAS, WE, an access address and the like based on the transfer information from the transfer target unit, and outputs the commands to the SDRAM 85, thereby realizing data transfer between the SDRAM 85 and the transfer-target unit which outputted the transfer information. The SDRAM 85 has features similar to those of a typical SDRAM described earlier, and is controlled by the control commands acquired from the SDRAM controller 235.
However, in controlling the SDRAM 85 in the conventional memory control unit structured as described above (see FIG. 29), the performance of the SDRAM can not be effectively utilized in some cases depending on conditions of data transfer.
Such case arises when, in the SDRAM 85, where its memory area is divided into banks 0 and 1, a total of ten pieces of data which is data a1 and a2 existing in the bank 0 and data b1 to data b8 existing in the bank 1 are continuously read across a bank boundary as shown in FIG. 31, for example.
In this case, the data a2 in the bank 0 and the data b1 in the bank 1 cannot be simultaneously read, therefore the order of commands to be issued from the command generator 83 to the SDRAM 85 is determined as shown in FIG. 32. In FIG. 32, precharge commands to the banks 0 and 1 are represented by xe2x80x9cPaxe2x80x9d and xe2x80x9cPbxe2x80x9d, respectively, active commands to the banks 0 and 1 are represented by xe2x80x9cAaxe2x80x9d and xe2x80x9cAbxe2x80x9d, respectively, and read commands to the banks 0 and 1 are represented by xe2x80x9cRaxe2x80x9d and xe2x80x9cRbxe2x80x9d, respectively. Besides, it is assumed that CAS latency is xe2x80x9c3xe2x80x9d clocks, and a burst length is xe2x80x9c8xe2x80x9d data. Then, an interval in which a precharge command, an active command, and a read command can be issued to the same bank (that is an interval Paxe2x86x92Aaxe2x86x92Ra, or an interval Pbxe2x86x92Abxe2x86x92Rb), and an interval in which active commands are issued to the banks 0 and 1 (that is an interval Aa⇄Ab) are each 3 clocks since the intervals are constrained to the CAS latency which is a minimum transition time.
Referring to FIG. 32, the command generator 83 first issues the Pa command to the bank 0 including the data a1 and a2 to read the data (in the zeroth cycle). Since the Aa command cannot be continuously issued to the bank 0 due to the constraint of the CAS latency, the Pb command is issued to the bank 1 in the interval (in the first cycle). Afterwards, the Aa command is issued at the third clock from the issue of the Pa command (in the third cycle).
A command which can be issued next is the Ra command to the bank 0 or the Ab command to the bank 1, however, both commands must wait until three clocks have elapsed because of the constraint of the CAS latency. Note that there is such rule as the command generator 83 processes the control signals in the order that they are sent from the address generator 82. Accordingly, the command generator 83 issues the Ra command first after three clocks have elapsed (in the sixth cycle), and next issues the Ab command (in the seventh cycle). The Rb command, resultantly, is issued in the tenth cycle at the earliest.
By the processing described above, the data a1 and a2 are sequentially read from the ninth cycle which is at the third clock from the issue of the Ra command, and data b1 to b8 are sequentially read from the thirteenth cycle which is at the third clock from the issue of the Rb command. Accordingly, entire data reading is terminated in the twentieth cycle.
The conventional memory control unit, thus, has the fixed rule and constraint as described above. Therefore, since the data in the banks 0 and 1 cannot be continuously read (see the eleventh to twelfth cycles in FIG. 32), there occurs some cases that it takes a large amount of time to terminate the entire data reading. That is to say, when data is continuously transferred across the bank boundary from an arbitrary address in the SDRAM 85, such problem arises as the efficiency in data transfer is degraded due to the uniquely-determined procedure of issuing commands.
On the other hand, in the conventional memory system described above (FIG. 30), the SDRAM cannot be efficiently controlled in some cases.
FIG. 33 shows, column by column, numbers of pages including columns to be accessed in data transfer requested by transfer-target units, and numbers of banks to which the pages belong, in order that the columns are accessed. As shown in FIG. 33, it is assumed here that priority of data transfer becomes higher toward the upper transfer-target unit, and the transfer-target unit 231 requests for data transfer to alternatively access the page 0 in the bank 0 and the page 0 in the bank 1 four times in total in units of eight columns, the transfer-target unit 232 requests for data transfer to access the paged in the bank 1 twice in total in units of eight columns, and the transfer-target unit 233 requests for data transfer to access the page 1 in the bank 0 only once in eight columns.
FIG. 34 shows an order of the data transfer in operation clocks in the case where the data transfer as shown in FIG. 33 is simultaneously requested from the transfer-target units. It is assumed in FIG. 34 that the CAS latency is 3, and a burst length is 8. The CAS latency here represents latency (the number of clocks) from input of a read command to reading of the corresponding data. Also, the burst length here represents the number of words outputted or inputted in a read cycle or a write cycle. Since the CAS latency is 3 in the present example, read data until one clock after a precharge command is inputted is effective. Besides, it is assumed that an interval between a precharge command and an active command and an interval between an active command and a read command to the same bank must be both more than or equal to three clocks.
As shown in FIG. 34, data is transferred according to the priority, i.e., in order of the transfer-target unit 231, the transfer-target unit 232, and the transfer-target 233. In this example, a column to be transferred last in response to a request from the transfer-target unit 231 is included in the page 0 in the bank 1, and a column to be first transferred in response to a request from the transfer-target unit 232 is included in the page 1 in the bank 1. That is, the columns included in the different pages in the same bank are to be continuously accessed. Accordingly, since precharge and active processing cannot be performed while accessing the other bank, overhead is produced in the interval, thereby decreasing actual transfer rates.
Furthermore, when the SDRAM as described above is used as memory for temporarily storing decoded image data decoded by a video decoder decoding coded image data, or as memory for temporarily storing coded image data coded by a video encoder encoding image data, decoded image data or coded image data which extends across a plurality of banks is read in the decoding and encoding. In this case, however, the data is read in an order of address as in the conventional way, which often leads to a case where columns in different pages in the same bank are continuously accessed. As a result, there arises the same problem as in the above.
Therefore, an object of the present invention is to provide a memory control unit and method, and a medium containing a program for realizing the method which always optimizes an order of issuing commands to an SDRAM and an order of transferring data from/in each transfer-target unit in accordance with relation between contents to be accessed and a bank boundary so as to minimize a decrease in transfer rates and which can make full use of the data-transfer performance of the SDRAM.
Moreover, another object of the present invention is to provide a memory control unit and a medium containing a program for realizing the unit which optimizes an order of reading image data in a video decoder and a video encoder so as to minimize a decrease in transfer rates.
The present invention has the following features to attain the object above.
A first aspect of the present invention is directed to a memory control unit controlling synchronous memory composed of a plurality of banks for reading and writing data by using a clock, comprising:
a transfer-target device operable to output commands for data reading and data writing;
an address generating device operable to generate the commands, then generate previously-determined control signals in accordance with the commands, and output the number of transferred bytes of data to be first transferred by read access;
a command generating device operable to generate and output the clock, receive the control signals and the number of transferred bytes, then generating previously-determined control commands in accordance with the control signals to output, and thereby control the synchronous memory; and
a data processing device operable to receive the control commands, and mediate data transfer between the transfer-target device and the synchronous memory in accordance with the control commands;
the command generating device, in a case where data read processing is continuously performed to different banks of the plurality of banks across a bank boundary, controls an order of issuing a read command to a first bank and an active command to a subsequent bank according to the number of transferred bytes.
Here, according to a preferable second aspect, the command generating device in the first aspect issues the read commands to the first bank prior to the active command to the subsequent bank when the number of transferred bytes is larger than the minimum number of clocks for transition between commands, and issues the active command to the subsequent bank prior to the read command to the first bank when the number of transferred bytes is smaller than the minimum number of clocks for transition between commands.
As described above, in the first and second aspects, the command generating device controls the processing of the SDRAM by judging, based on the transferred bytes generated in the address generating device which is to be first issued between the read command to the first bank and the active command to the subsequent bank. In this way, in the case where data read processing is continuously performed to different banks, it is possible to issue commands so as to always terminate the data transfer in the minimum number of cycles. That is, the number of cycles required for two continuous access can be reduced, thereby increasing effective transfer rates of the SDRAM.
A third aspect is directed to a memory control unit controlling synchronous memory composed of a plurality of banks for reading and writing data with using a clock, comprising:
a transfer-target device operable to output commands for data reading and data writing;
an address generating device operable to receive the commands, then generate previously-determined control signals in accordance with the commands to output, and output a transfer size of read data in one bank of the plurality of banks to which processing is to be performed;
a command generating device operable to generate and output the clock, receive the control signals, then generate previously-determined control commands in accordance with the control signals to output, and thereby control the synchronous memory;
a counter operable to count the number of times of issuing read commands by the command generating device, and receive the transfer size to subtract a burst length from the transfer size with each count; and
a data processing device operable to receive the control commands, and mediate data transfer between the transfer-target device and the synchronous memory in accordance with the control commands;
the counter, when the transfer size after the subtraction becomes not more than the burst length, notifying the command generating device of the fact, and in response to the notification, the command generating device issues a next read command as a read command with precharge for automatically performing precharge processing after read processing is terminated.
As described above, in the third aspect, the counter counts the number of times of issuing read commands by the command generating device. The data transfer performed at the last in one bank of the plurality of banks to which processing is to be performed is thus detected, and the command generating device issues the read command with precharge in accordance with the result of the detection, to control the processing of the SDRAM. Then, in the bank in which the command with precharge is issued, after the read processing for one data is completed, the precharge processing for the other data is automatically performed, thereby making it possible to start the precharge processing without delay even when the timing of issuing the precharge command matches the timing of issuing the subsequent other command. As a result, the effective transfer rates of the SDRAM can be increased.
A fourth aspect is directed to a memory control method of controlling synchronous memory composed of a plurality of banks for reading and writing data with using a clock, comprising, when data read processing is continuously performed to different banks of the plurality of banks across a bank boundary, the following:
outputting commands for the data read processing;
receiving the commands, then generating previously-determined control signals in accordance with the commands to output, and outputting the number of transferred bytes of data to be first transferred by read access; and
generating control commands based on the control signals and the number of transferred bytes to issue, and at the same time, controlling an order of issuing a read command to a first bank and an active command to a subsequent bank according to the number of transferred bytes.
Here, according to a preferable fifth aspect, the generating and outputting of the control commands in the fourth aspect issues the read command to the first bank prior to the active command to the subsequent bank when the number of transferred bytes is larger than the minimum number of clocks for transition between commands, and issues the active command to the subsequent bank prior to the read command to the first bank when the number of transferred bytes is smaller than the minimum number of clocks for transition between commands.
As described above, in the fourth and fifth aspects, it is judged, based on the number of bytes of data first transferred by read access, which is to be first issued between the read command to the first bank and the active command to the subsequent bank, to control the processing of the SDRAM. In this way, in the case where data read processing is continuously performed to different banks, it is possible to issue commands so as to always terminate the data transfer in the minimum number of cycles. That is, the number of cycles required for two continuous access can be reduced, thereby increasing the effective transfer rates of the SDRAM.
A sixth aspect is directed to a memory control method of controlling synchronous memory composed of a plurality of banks for reading and writing data with using a clock, comprising:
outputting commands for data reading and data writing;
generating previously-determined control signals in accordance with the commands to output, and outputting a transfer size of read data in one bank of the plurality of banks to which processing is to be performed;
counting the number of times of issuing read commands to the synchronous memory;
subtracting a burst length from the transfer size with each count, and outputting a previously-determined notification when the transfer size after the subtraction becomes not more than the burst length; and
generating control commands based on the control signals and the notification, and at the same time, when receiving the notification, issuing a next read command as a read command with precharge for automatically performing precharge processing after read processing is terminated.
As described above, in the sixth aspect, the number of times of issuing read commands to the SDRAM is counted. The data transfer performed at the last in one bank of the plurality of banks to which processing is to be performed is thus detected, the read command with precharge is issued in accordance with the result of the detection, to control the processing of the SDRAM. Then, in the bank in which the command with precharge is issued, after the read processing for one data is completed, the precharge processing for the other data is automatically performed, thereby making it possible to start the precharge processing without delay even when the timing of issuing the precharge command matches the timing of issuing the subsequent other command. As a result, the effective transfer rates of the SDRAM can be increased.
A seventh aspect is directed to a memory control unit for controlling memory having memory areas divided into a plurality of banks, wherein:
each of the plurality of banks being split in a plurality of split banks;
a delay developing in the memory when access to memory areas in different split banks in a same bank is continuous; and
wherein the memory control unit comprises:
an accepting device operable to accept, from an external apparatus, access information indicating two or more memory areas in a bank or banks to be accessed by a plurality of unit access;
an optimizing device operable to optimize and decide an order of access of the plurality of unit access based on whether the memory areas for the plurality of unit access indicated by the access information are in the same bank or different banks so as to decrease frequency of continuous access to the memory areas in the same bank; and
a control device operable to control the memory so that the memory area in the memory is accessed according to the access order optimized and decided by the optimizing device.
As described above, in the seventh aspect, it is possible to decrease the frequency of continuous access to the same bank. Therefore, the overhead due to precharge processing and the like can be reduced, to increase the effective transfer rates of the SDRAM.
According to an eighth aspect, in the seventh aspect, the optimizing device optimizes and decides the order of access of the plurality of unit access based on whether the memory areas for the plurality of unit access indicated by the access information are in the same bank or different banks and in the same split bank or different split banks so as to decrease frequency of continuous access not to memory areas in the same bank but to memory areas in different split banks in the same bank.
As described above, according to the eighth aspect, in the seventh aspect, it is possible to decrease the frequency of continuous access to different pages in the same bank.
According to a ninth aspect, in the seventh aspect, the external apparatus is constituted by one or more transfer-target units, the access information is composed of two or more specific access information issued from the transfer-target units, each of the specific access information is composed of the one or more unit access, and the optimizing device comprises:
a tail specifying device operable to specify a tail bank to be accessed at the last in currently-accessed specific access information or in preceding specific access information to be accessed first;
a head specifying device operable to specify a head bank to be accessed first in each of the specific access information; and
a selecting device operable to select access to a memory area indicated by specific access information corresponding to the head bank representing a different bank from the tail bank prior to access to a memory area indicated by specific access information corresponding to the head bank representing the same bank as the tail bank, and define an order of access immediately after access to a memory area indicated by the preceding specific access information.
As described above, according to the ninth aspect, in the seventh aspect, it is possible, when accepting two or more access information, to give first priority to the access information which first accesses to the bank different from the bank to be accessed at the last in the access information to be first accessed.
According to a tenth aspect, in the ninth aspect, the tail specifying device further specifies a tail split bank to be accessed at the last in the preceding specific access information, the head specifying device further specifies a head split bank to be accessed first in each of the specific access information, and the selecting device selects access to the memory area indicated by the specific access information corresponding to the head bank representing a different bank from the tail bank and access to a memory area indicated by specific access information corresponding to the head split bank representing the same split bank as the tail split bank, prior to an access to a memory area indicated by specific access information corresponding to the head bank representing the same bank as the tail bank and also corresponding to the head split bank representing a different split bank from the tail split bank, and defines the order of access immediately after the access to the memory area indicated by the preceding specific access information.
As described above, according to the tenth aspect, in the ninth aspect, it is possible, when accepting two or more access information, to give first priority to the access information which first accesses to the bank different from a bank to be accessed at the last in the access information to be first accessed, and the same page in the same bank as the bank to be accessed at the last in the access information to be first accessed.
According to eleventh and twelfth aspects, respectively in the ninth and tenth aspects, the specific access information each includes limit information indicating time limits for transfer pending, and the selecting device judges whether each of the specific access information is to exceed the limits indicated by the limit information or not, and selects with the highest priority access to a memory area indicated by specific access information judged to most likely exceed the limits.
As described above, according to the eleventh and twelfth aspects, respectively in the ninth and tenth aspects, it is judged whether each access information is to exceed the limit or not. When judged to likely exceed, the corresponding access information can be selected with the highest priority. Therefore, the overhead due to precharge processing and the like is reduced while assuring real time characteristics of each access information to some extent, thereby increasing the effective transfer rates of the SDRAM.
According to thirteenth and fourteenth aspects, respectively in the eleventh and twelfth aspects, the memory comprises amplifiers operable to transfer each provided for each of the banks for holding data in one predetermined split bank, and access to the memory area in the memory is always made through the amplifiers for transfer, the delay is a sum of xe2x80x9ctime required to transfer data held in an amplifier for transfer to one split bank which is accessed just beforexe2x80x9d and xe2x80x9ctime required to transfer data stored in one split bank which is currently accessed to an amplifier for transferxe2x80x9d, the limit information is the number of limit cycles representing limits for the number of cycles permitted from when specific access information is issued to when transfer is completed, and the selecting device includes:
a remaining-cycle-number holding device operable to hold, for each of the specific access information, the number of remaining cycles representing limits for the number of cycles permitted from a present time to when transfer is completed;
an initial-value setting device operable to make the remaining-cycle-number holding device hold the number of limit cycles as an initial value of the number of remaining cycles when specific access information is issued;
a subtraction device operable to subtract one from the number of remaining cycles held in the remaining-cycle-number holding device in one cycle unit;
a calculation device operable to calculate for each of the specific access information xe2x80x9c(the number of cycles required until currently-executed access is completed)+(the number of cycles required to access specific access information selected with higher priority)+(the number of cycles required to transfer data held in an amplifier for transfer to one predetermined split bank)+(the number of cycles required to transfer data stored in one predetermined split bank to an amplifier for transfer)+(the number of cycles required for its own access)=the number for prospective cycles for completionxe2x80x9d by time when the currently-executed access is completed; and
a judging device operable to judge, in a case of xe2x80x9cthe number of prospective cycles for completion greater than the number of remaining cyclesxe2x80x9d, that corresponding specific access information is to exceed the limits.
As described above, according to the thirteenth and fourteenth aspects, respectively in the eleventh and twelfth aspects, the number of limit cycles is defined for each access information as an initial value of the number of remaining cycles. Then, one is subtracted from the number of remaining cycles in one cycle unit, and the result is compared with the number of cycles required for access by the other access information selected with the higher priority. Then, it is judged whether the access information is to exceed the limits or not in the case where it is selected after the access by the other access information selected with the higher priority is terminated. The access information judged to likely exceed the limits can be selected with the highest priority. Therefore, the overhead due to the precharge processing and the like is reduced while assuring the real time characteristics of each access information even when the access information is selected after the access by the other access information is terminated, thereby increasing the effective transfer rates of the SDRAM.
According to fifteenth and sixteenth aspects, respectively in the eleventh and twelfth aspects, the memory comprises amplifiers for transfer, each provided for each of the banks for holding data in one predetermined split bank, and access to the memory area in the memory is always made through the amplifiers for transfer, the delay is a sum of xe2x80x9ctime required to transfer data held in an amplifier for transfer to one split bank which is accessed just beforexe2x80x9d and xe2x80x9ctime required to transfer data stored in one split bank which is currently accessed to an amplifier for transferxe2x80x9d, the limit information is the number of limit cycles representing limits for the number of cycles permitted from when specific access information is issued to when transfer is completed, and the selecting device includes:
a counting device operable to count for each of the specific access information the number of queued cycles in one cycle unit since the specific access information is issued;
a calculation device operable to calculate for each of the specific access information xe2x80x9c(the number of queued cycles)+(the number of cycles required until currently-executed access is completed)+(the number of cycles required to access specific access information selected with higher priority)+(the number of cycles required to transfer data held in an amplifier for transfer to one predetermined split bank)+(the number of cycles required to transfer data stored in one predetermined split bank to an amplifier for transfer)+(the number of cycles required for its own access)=the number of prospective cycles for completionxe2x80x9d by time when the currently-executed access is completed; and
a judging operable to judge, in a case of xe2x80x9cthe number of prospective cycles for completion greater than the number of limit cyclesxe2x80x9d, that corresponding specific access information is to exceed the limits.
As described above, according to the fifteenth and sixteenth aspects, respectively in the eleventh and twelfth aspects, the number of queued cycles is counted for each access information, and thereby it is judged whether the access information is to exceed the limits even after the access by the other access information selected with the higher priority is terminated. Thus, the access information judged to likely exceed the limits can be selected with the highest priority. Therefore, the overhead due to the precharge processing and the like is reduced while assuring the real time characteristics of each access information even when the access information is selected after the access by the other access information is terminated, thereby increasing the effective transfer rates of the SDRAM.
According to a seventeenth aspect, in the seventh aspect, the external apparatus is a video decoding apparatus decoding coded image data, or a video encoding apparatus encoding image data, generated image data is temporarily stored in the memory, and then part of the image data stored in the memory which is continuous in a display state thereof is read to generate new image data, the generated image data is distributed in unit areas in the memory each composed of a memory area in a single split bank, and stored in predetermined order that the unit areas are continuous in the display state, unit areas contiguous to each other in storage order are composed of different banks or the same split bank, the access information indicates a memory area including unit areas contiguous to each other in the display state and in the storage order, and unit areas contiguous to each other in the display state but not contiguous in the storage order, and is issued from the video decoding apparatus or the video encoding apparatus to generate new image data, and the optimizing device includes:
a dividing device operable to divide a memory area indicated by the access information into continuous single split bank areas each of which is a memory area in a single split bank;
a non-contiguous-boundary detecting device operable to detect a non-contiguous boundary representing a boundary between unit areas contiguous to each other in the display state but not contiguous in the storage order; and
a relative-order deciding device operable to decide an order of access to the single split bank areas based on whether the unit areas contiguous to each other across the non-contiguous boundary are composed of the same bank or different banks.
As described above, according to the seventeenth aspect, in the seventh aspect, the order of access to single-page areas based on whether the unit areas contiguous to each other across the non-contiguous boundary are composed of the same bank or different banks.
According to an eighteenth aspect, in the seventeenth aspect, the relative-order deciding device defines order of access to the single split bank areas below the non-contiguous boundary as the same as order of access to the single split bank areas above the non-contiguous boundary when the unit areas contiguous to each other across the non-contiguous boundary are composed of the same bank, and defines the access order as the reverse when the unit areas are composed of different banks.
As described above, according to the eighteenth aspect, in the seventeenth aspect, the order of access to the single-page areas below the non-contiguous boundary can be optimized by defining it as the same as the order of access to the singlepage areas above the non-contiguous boundary when the unit areas contiguous to each other across the non-contiguous boundary are composed of the same bank, and as the reverse to the order of access to the single-page areas above the noncontiguous boundary when the unit areas are composed of different banks.
According to a nineteenth aspect, in the seventh aspect, the external apparatus is a video decoding apparatus decoding coded image data, or a video encoding apparatus encoding image data, generated image data is temporarily stored in the memory, and then part of the image data stored in the memory which is continuous in a display state thereof is read to generate new image data, the generated image data is distributed in unit areas in the memory each composed of a memory area in a single split bank, and stored in predetermined order that the unit areas are continuous in the display state, unit areas contiguous to each other in storage order are composed of different banks or the same split bank, the access information indicates a memory area including unit areas contiguous to each other in the display state and in the storage order, and unit areas contiguous to each other in the display state but not contiguous in the storage order, and is issued from the video decoding apparatus or the video encoding apparatus to generate new image data, and the optimizing device includes:
a dividing device operable to divide a memory area indicated by the access information into continuous single split bank areas each of which is a memory area in a single split bank;
a non-contiguous-boundary detecting device operable to detect a non-contiguous boundary representing a boundary between unit areas contiguous to each other in the display state but not contiguous in the storage order;
an address converting device operable to convert between a logical address in the image data and a physical address in the memory so that the unit areas contiguous to each other across the non-contiguous boundary are composed of different banks when the unit areas are composed of the same bank in a case where the generated image data is stored in predetermined order that the image data is continuous in the display state; and
an order reversing device operable to define order of access to the single split bank areas below the non-contiguous boundary as the reverse to order of access to the single split bank areas above the non-contiguous boundary.
As described above, according to the nineteenth aspect, in the seventh aspect, when the generated image data is stored in the order that the image data is continuous in the display state, it is possible to convert between the logical address in the image data and the physical address in the memory so that the unit areas contiguous to each other across the non-contiguous boundary, when composed of the same bank, are composed of different banks. Therefore, in this case, the overhead due to precharge processing and the like is reduced, to increase the effective transfer rates of the SDRAM.
According to twentieth to twenty-second aspects, respectively in the seventeenth to nineteenth aspects, the optimizing device further includes:
a screen-size setting device operable to set the number of pixels which are continuous in the storage order and in the display state in image data to be stored in the memory as a screen size;
a configuration setting device operable to set a shape of the unit area; and
a bank judging device operable to judge whether the unit areas contiguous to each other across the non-contiguous boundary are composed of the same bank or different banks based on the screen size and the shape in the case where the generated image data is stored in predetermined order that the image data is continuous in the display state.
As described above, according to the twentieth to twenty-second aspects, respectively in the seventeenth to nineteenth aspects, when the generated image data is stored in the order the image data is continuous in the display state, it is possible to judge based on the screen size of the image data and the shape of the unit area whether the unit areas contiguous across the contiguous boundary are composed of the same bank or different banks. Therefore, the overhead due to the precharge processing and the like is reduced according to the screen size of the image data and the shape of the unit area, thereby increasing the effective transfer rates of the SDRAM.
According to twenty-third to twenty-eighth aspects, respectively in the seventeenth to twenty-second aspects, the optimizing device further includes:
a contiguous-boundary detecting device operable to detect a contiguous boundary representing a boundary between the unit areas contiguous to each other in the display state and in the storage order;
a comparing device operable to compare size of memory areas obtained by dividing the memory area indicated by the access information by the contiguous boundary; and
an initial-order deciding device operable to define order of access to the single split bank areas above the non-contiguous boundary as order that single split bank areas belonging to a memory area judged to be smaller by the comparison made by the comparing device are read first.
As described above, according to the twenty-third to twenty-eighth aspects, respectively in the seventeenth to twenty-second aspects, the order of access to single-page areas above the non-contiguous boundary can be defined as the order that the single-page areas belonging to the small memory area are first read. Therefore, the overhead due to the precharge processing and the like is reduced, to increase the effective transfer rates of the SDRAM.
A twenty-ninth aspect is directed to a recording medium, capable of reading from a computer, containing a program executed in the computer that is a program for realizing in the computer operational environment, when in synchronous memory composed of a plurality of banks for reading and writing data with using a clock, data read processing is continuously performed to different banks of the plurality of banks across a bank boundary, comprising:
outputting commands for the data read processing;
receiving the commands, then generating previously-determined control signals in accordance with the commands to output, and outputting the number of transferred bytes of data to be first transferred by read access; and
issuing control commands based on the control signals and the number of transferred bytes, and at the same time, controlling order of issuing a read command to a first bank and an active command to a subsequent bank according to the number of transferred bytes.
According to a thirtieth aspect, in the twenty-ninth aspect, the generating and outputting of the control commands issues the read command to the first bank prior to the active command to the subsequent bank when the number of transferred bytes is larger than the minimum number of clocks for transition between commands, and issues the active command to the subsequent bank prior to the read command to the first bank when the number of transferred bytes is smaller than the minimum number of clocks for transition between commands.
A thirty-first aspect is directed to a recording medium, capable of reading from a computer, containing a program executed in the computer that is a program for realizing in the computer operational environment, in synchronous memory composed of a plurality of banks for reading and writing data with using a clock, comprising:
outputting commands for data reading and data writing;
generating previously-determined control signals in accordance with the commands to output, and outputting a transfer size of read data in one bank of the plurality of banks to which processing is to be performed;
counting the number of times of issuing read commands to the synchronous memory;
subtracting a burst length from the transfer size with each count, and outputting a previously-determined notification when the transfer size after the subtraction becomes not more than the burst length; and
issuing control commands based on the control signals and the notification, and at the same time, when receiving the notification, issuing a next read command as a read command with precharge for automatically performing precharge processing after read processing is terminated.
A thirty-second aspect is directed to a recording medium, capable of reading from a computer, containing a program executed in the computer that is a program for realizing in the computer operational environment, when controlling memory, having a memory area divided into a plurality of banks each divided into a plurality of split banks, in which a delay develops due to continuous access to memory areas in different split banks in the same bank, comprising:
accepting, from an external apparatus, access information indicating two or more memory areas in a bank or banks to be accessed by a plurality of unit access;
optimizing and deciding order of access of the plurality of unit access based on whether the memory areas for the plurality of unit access indicated by the access information are in the same bank or different banks and in the same split bank or different split banks so as to decrease frequency of continuous access to the memory areas in the same bank; and
controlling the memory so that the memory area in the memory is accessed according to the access order optimized and decided by the optimizing.
According to a thirty-third aspect, in the thirty-second aspect, the optimizing and deciding optimizes and decides the order of access of the plurality of unit access based on whether the memory areas for the plurality of unit access is indicated by the access information are in the same bank or different banks so as to decrease frequency of continuous access not to memory areas in the same bank but to memory areas in different split banks in the same bank.
According to a thirty-fourth aspect, in the thirty-second aspect, the external apparatus is constituted by one or more transfer-target units, the access information is composed of two or more specific access information issued from the transfer-target units, each of the specific access information is composed of the one or more unit access, and the optimizing and deciding step further includes:
specifying a tail bank to be accessed at the last in currently-accessed specific access information or in preceding specific access information to be accessed first;
specifying a head bank to be accessed first in each of the specific access information; and
selecting access to a memory area indicated by specific access information corresponding to the head bank representing a different bank from the tail bank prior to access to a memory area indicated by specific access information corresponding to the head bank representing the same bank as the tail bank, and defining order of access immediately after access to a memory area indicated by the preceding specific access information.
According to a thirty-fifth aspect, in the thirty-fourth aspect, the tail-specifying step further specifies a tail split bank to be accessed at the last in the preceding specific access information, the head-specifying step further specifies a head split bank to be accessed first in each of the specific access information, and the order-defining step selects access to the memory area indicated by the specific access information corresponding to the head bank representing a different bank from the tail bank and access to a memory area indicated by specific access information corresponding to the head split bank representing the same split bank as the tail split bank, prior to access to a memory area indicated by specific access information corresponding to the head bank representing the same bank as the tail bank and also corresponding to the head split bank representing a different split bank from the tail split bank, and defines the order of access immediately after the access to the memory area indicated by the preceding specific access information.
According to thirty-sixth and thirty-seventh aspects, respectively in the thirty-fourth and thirty-fifth aspects, the specific access information each includes limit information indicating time limits for transfer pending, and the order-defining step judges whether each of the specific access information is to exceed the limits indicated by the limit information or not, and selects with the highest priority access to a memory area indicated by specific access information judged to most likely exceed the limits.
According to thirty-eighth and thirty-ninth aspects, respectively in the thirty-sixth and thirty-seventh aspects, the memory comprises amplifiers for transfer each provided for each of the banks for holding data in one predetermined split bank, and access to the memory area in the memory is always made through the amplifiers for transfer, the delay is a sum of xe2x80x9ctime required to transfer data held in an amplifier for transfer to one split bank which is accessed just beforexe2x80x9d and xe2x80x9ctime required to transfer data stored in one split bank which is currently accessed to an amplifier for transferxe2x80x9d, the limit information is the number of limit cycles representing limits for the number of cycles permitted from when specific access information is issued to when transfer is completed, and the order-defining further includes:
holding for each of the specific access information the number of remaining cycles representing limits for the number of cycles permitted from a present time to when transfer is completed;
making the holding hold the number of limit cycles as an initial value of the number of remaining cycles when specific access information is issued;
subtracting one from the number of remaining cycles held in the holding in one cycle unit;
calculating for each of the specific access information xe2x80x9c(the number of cycles required until currently-executed access is completed)+(the number of cycles required to access specific access information selected with higher priority)+(the number of cycles required to transfer data held in an amplifier for transfer to one predetermined split bank)+(the number of cycles required to transfer data stored in one predetermined split bank to an amplifier for transfer)+(the number of cycles required for its own access)=the number for prospective cycles for completionxe2x80x9d by time when the currently-executed access is completed; and
judging, in a case of xe2x80x9cthe number of prospective cycles for completion greater than the number of remaining cyclesxe2x80x9d, that corresponding specific access information is to exceed the limits.
According to fortieth and forty-first aspects, respectively in the thirty-sixth and thirty-seventh aspects, the memory comprises amplifiers for transfer, each provided for each of the banks for holding data in one predetermined split bank, and access to the memory area in the memory is always made through the amplifiers for transfer, the delay is a sum of xe2x80x9ctime required to transfer data held in an amplifier for transfer to one split bank which is accessed just beforexe2x80x9d and xe2x80x9ctime required to transfer data stored in one split bank which is currently accessed to an amplifier for transferxe2x80x9d, the limit information is the number of limit cycles representing limits for the number of cycles permitted from when specific access information is issued to when transfer is completed, and the order-defining further includes:
counting for each of the specific access information the number of queued cycles in one cycle unit since the specific access: information is issued;
calculating for each of the specific access information xe2x80x9c(the number of queued cycles)+(the number of cycles required until currently-executed access is completed)+(the number of cycles required to access specific access information selected with higher priority)+(the number of cycles required to transfer data held in an amplifier for transfer to one predetermined split bank)+(the number of cycles required to transfer data stored in one predetermined split bank to an amplifier for transfer)+(the number of cycles required for its own access)=the number of prospective cycles for completionxe2x80x9d by time when the currently-executed access is completed; and
judging, in a case of xe2x80x9cthe number of prospective cycles for completion greater than the number of limit cyclesxe2x80x9d, that corresponding specific access information is to exceed the limits.
According to a forty-second aspect, in the thirty-second aspect, the external apparatus is a video decoding apparatus decoding coded image data, or a video encoding apparatus encoding image data, generated image data is temporarily stored in the memory, and then part of the image data stored in the memory which is continuous in a display state thereof is read to generate new image data, the generated image data is distributed in unit areas in the memory each composed of a memory area in a single split bank, and stored in predetermined order that the unit areas are continuous in the display state, unit areas contiguous to each other in storage order are composed of different banks or the same split bank, the access information indicates a memory area including unit areas contiguous to each other in the display state and in the storage order, and unit areas contiguous to each other in the display state but not contiguous in the storage order, and is issued from the video decoding apparatus or the video encoding apparatus to generate new image data, and the optimizing and deciding further includes:
dividing a memory area indicated by the access information into continuous single split bank areas each of which is a memory area in a single split bank;
detecting a non-contiguous boundary representing a boundary between unit areas contiguous to each other in the display state but not contiguous in the storage order; and
deciding order of access to the single split bank areas based on whether the unit areas contiguous to each other across the non-contiguous boundary are composed of the same bank or different banks.
According to a forty-third aspect, in the forty-second aspect, the deciding defines order of access to the single split bank areas below the non-contiguous boundary as the same as order of access to the single split bank areas above the non-contiguous boundary when the unit areas contiguous to each other across the non-contiguous boundary are composed of the same bank, and defines the access order as the reverse when the unit areas are composed of different banks.
According to a forty-fourth aspect, in the thirty-second aspect, the external apparatus is a video decoding apparatus decoding coded image data, or a video encoding apparatus encoding image data, generated image data is temporarily stored in the memory, and then part of the image data stored in the memory which is continuous in a display state thereof is read to generate new image data, the generated image data is distributed in unit areas in the memory each composed of a memory area in a single split bank, and stored in predetermined order that the unit areas are continuous in the display state, unit areas contiguous to each other in storage order are composed of different banks or the same split bank, the access information indicates a memory area including unit areas contiguous to each other in the display state and in the storage order, and unit areas contiguous to each other in the display state but not contiguous in the storage order, and is issued from the video decoding apparatus or the video encoding apparatus to generate new image data, and the optimizing and deciding further includes:
dividing a memory area indicated by the access information into continuous single split bank areas each of which is a memory area in a single split bank;
detecting a non-contiguous boundary representing a boundary between unit areas contiguous to each other in the display state but not contiguous in the storage order;
converting between a logical address in the image data and a physical address in the memory so that the unit areas contiguous to each other across the non-contiguous boundary are composed of different banks when the unit areas are composed of the same bank in a case where the generated image data is stored in predetermined order that the image data is continuous in the display state; and
defining order of access to the single split bank areas below the non-contiguous boundary as the reverse to order of access to the single split bank areas above the non-contiguous boundary.
According to forty-fifth to forty-seventh aspects, respectively in the forty-second to forty-fourth aspects, the optimizing and deciding further includes:
setting the number of pixels which are continuous in the storage order and in the display state in image data to be stored in the memory as a screen size;
setting a shape of the unit area; and
judging whether the unit areas contiguous to each other across the non-contiguous boundary are composed of the same bank or different banks based on the screen size and the shape in the case where the generated image data is stored in predetermined order that the image data is continuous in the display state.
According to forty-eighth to fifth-third aspects, respectively in the forty-second to forty-seventh aspects, the optimizing and deciding further includes:
detecting an contiguous boundary representing a boundary between the unit areas contiguous to each other in the display state and in the storage order;
comparing size of memory areas obtained by dividing the memory area indicated by the access information by the contiguous boundary; and
defining order of access to the single split bank areas above the non-contiguous boundary as order that single split bank areas belonging to a memory area judged to be smaller by the comparison made by the comparing means are read first.
As described above, the twenty-ninth to fifty-third aspects are directed to a recording medium containing a program for realizing functions in the first to twenty-eighth aspects. By using the medium, the functions described in the first to twenty-eighth aspects can be realized as a software in a computer, to obtain the same effects as in the above.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.